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4M x 36-Bit Dynamic RAM Module
HYM 364020S/GS-60
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SIMM modules with 4 194 304 words by 36-Bit organization for PC main memory applications Fast access and cycle time 60 ns access time 110 ns cycle time (-60 version) Fast page mode capability 40 ns cycle time (-60 version) Single + 5 V ( 10 %) supply Low power dissipation max. 7260 mW active (-60 version) CMOS - 66 mW standby TTL -132 mW standby CAS-before-RAS refresh RAS-only-refresh Hidden-refresh 12 decoupling capacitors mounted on substrate All inputs, outputs and clocks fully TTL compatible 72 pin Single in-Line Memory Module (L-SIM-72-12) with 22.9 mm (900 mil) height Utilizes eight 4Mx4-DRAMs and four 4Mx1-DRAMs in SOJ packages 2048 refresh cycles / 32 ms Optimized for use in byte-write parity applications Tin-Lead contact pads (S-version) Gold contact pads (GS - version)
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Semiconductor Group
1
6.95
HYM 364020S/GS-60 4M x 36-Bit
The HYM 364020S/GS-60 is a 16 MByte DRAM module organized as 4 194 304 words by 36Bit in a 72-pin single-in-line package comprising eight HYB 5117400BJ 4M x 4 DRAMs and four HYB 514100BJ 4M x 1 DRAMS in 300 mil wide SOJ-packages mounted together with twelve 0.2 F ceramic decoupling capacitors on a PC board. The HYM 364020S/GS-60 can also be used as a 8 388 608 words by 18-bits dynamic RAM module by means of connecting DQ0 and DQ18, DQ1 and DQ19, DQ2 and DQ20, ... , DQ17 and DQ35, respectively. Each HYB 5117400BJ and HYB 514100BJ is described in the data sheet and is fully electrical tested and processed according to SIEMENS standard quality procedure prior to module assembly. After assembly onto the board, a further set of electrical tests is performed. The speed of the module can be detected by the use of four presence detect pins. The common I/O feature on the HYM 364020S/GS-60 dictates the use of early write cycles. Ordering Information Type HYM 364020S-60 HYM 364020GS-60 Ordering Code Q67100-Q2006 Q67100-Q982 Package L-SIM-72-12 L-SIM-72-12 Description DRAM Module (access time 60 ns) DRAM Module (access time 60 ns)
Semiconductor Group
2
HYM 364020S/GS-60 4M x 36-Bit
Pin Configuration
Pin Names
VSS DQ18 DQ19 DQ20 DQ21 N.C. A1 A3 A5 A10 DQ22 DQ23 DQ24 DQ25 N.C. A8 N.C. DQ26 1 DQ0 2 3 DQ1 4 5 DQ2 6 7 DQ3 8 9 VCC 10 11 A0 12 13 A2 14 15 A4 16 17 A6 18 19 DQ4 20 21 DQ5 22 23 DQ6 24 25 DQ7 26 27 A7 28 29 VCC 30 31 A9 32 33 RAS2 34 35 DQ8 36
A0-A10 DQ0-DQ35 CAS0 - CAS3 RAS0, RAS2 WE
Address Inputs Data Input/Output Column Address Strobe Row Address Strobe Read/Write Input Power (+ 5 V) Ground Presence Detect Pin No Connection
VCC VSS
PD N.C.
DQ17 VSS CAS2 CAS1 N.C. WE DQ9 DQ10 DQ11 DQ12 DQ13 VCC DQ14 DQ15 DQ16 PD0 PD2 N.C.
37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71
DQ35 38 CAS0 40 CAS3 42 RAS0 44 N.C. 46 N.C. 48 DQ27 50 DQ28 52 DQ29 54 DQ30 56 DQ31 58 DQ32 60 DQ33 62 DQ34 64 N.C. 66 PD1 68 PD3 70 VSS 72
Presence Detect Pins -60 PD0 PD1 PD2 PD3
VSS
N.C. N.C. N.C.
Semiconductor Group
3
HYM 364020S/GS-60 4M x 36-Bit
RAS0 CAS0 DQ0-DQ3 CAS RAS I/O1-I/O4 OE D0 CAS RAS I/O1-I/O4 OE D1 Di Do CAS RAS M0
DQ4-DQ7 DQ8 CAS1 DQ9-DQ12
CAS RAS I/O1-I/O4 OE D2 CAS RAS I/O1-I/O4 OE D3 Di Do CAS RAS M1
DQ13-DQ16 DQ17 RAS2 CAS2
DQ18-DQ21 DQ22-DQ25 DQ26 CAS3
CAS RAS I/O1-I/O4 OE D4 CAS RAS I/O1-I/O4 OE D5 Di Do CAS RAS M2
DQ27-DQ30 DQ31-DQ34
CAS RAS I/O1-I/O4 OE D6 CAS RAS I/O1-I/O4 D7 OE Di Do CAS RAS M3 VCC VSS C0 - C11
DQ35 A0-A10 WE D0-D7, M0-M3 D0-D7, M0-M3
Block Diagram
Semiconductor Group
4
HYM 364020S/GS-60 4M x 36-Bit
Absolute Maximum Ratings Operation temperature range ......................................................................................... 0 to + 70 C Storage temperature range......................................................................................... - 55 to 125 C Input/output voltage ............................................................................ -0.5V to min (Vcc+0.5, 7.0) V Power supply voltage...................................................................................................... - 1 to + 7 V Power dissipation..................................................................................................................... 9.3 W Data out current (short circuit) ................................................................................................ 50 mA Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage of the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC Characteristics TA = 0 to 70 C, VCC = 5 V 10 % Parameter Input high voltage Input low voltage Output high voltage (IOUT = - 5 mA) Output low voltage (IOUT = 4.2 mA) Input leakage current (0 V < VIN < 6.5 V, all other pins = 0 V) Output leakage current (DO is disabled, 0 V < VOUT < 5.5 V) Average VCC supply current (RAS, CAS, address cycling, tRC = tRC min) -60 version Symbol Limit Values min. max. Vcc+0.5 0.8 - 0.4 20 10 V V V V A A 2.4 - 0.5 2.4 - - 20 - 10 Unit Test Condition
1) 1) 1) 1) 1)
VIH VIL VOH VOL II(L) IO(L) ICC1
1)
-
1320
mA
2),3),4)
Standby VCC supply current (RAS = CAS = VIH) Average VCC supply current during RAS only refresh cycles (RAS cycling, CAS = VIH, tRC = tRC min) -60 version
ICC2 ICC3
-
24
mA
-
1320
mA
2),4)
Semiconductor Group
5
HYM 364020S/GS-60 4M x 36-Bit
DC Characteristics1) (cont' d) Parameter Average VCC supply current during fast page mode (RAS = VIL, CAS, address cycling, tPC = tPC min) -60 version Symbol Limit Values min. max. Unit Test Condition
ICC4
-
920
mA mA mA
2),3),4)
Standby VCC supply current (RAS = CAS = VCC - 0.2 V) Average VCC supply current during CAS-before-RAS refresh mode (RAS, CAS cycling, tRC = tRC min) -60 version
ICC5 ICC6
-
12
-
2),4)
Capacitance TA = 0 to 70 C, VCC = 5 V 10 %, f = 1 MHz Parameter Input capacitance (A0 to A10, WE) Input capacitance (RAS0, RAS2) Input capacitance (CAS0 - CAS3) I/O capacitance (DQ0-DQ7,DQ9-DQ16,DQ18-DQ25,DQ27-DQ34) I/O capacitance (DQ8,DQ17,DQ26,DQ35) Symbol Limit Values min. max. 75 45 25 15 25 pF pF pF pF pF - - - - - Unit
CI1 CI2 CI3 CIO1 CIO2
Semiconductor Group
6
HYM 364020S/GS-60 4M x 36-Bit
AC Characteristics 5)6) TA = 0 to 70 C,VCC = 5 V 10 %, tT = 5 ns Parameter
Symbol
Limit Values -60 min. max. - - 10k 10k - - - - 45 30 - - - 50 32
Unit
Note
common parameters
Random read or write cycle time RAS precharge time RAS pulse width CAS pulse width Row address setup time Row address hold time Column address setup time Column address hold time RAS to CAS delay time RAS to column address delay time RAS hold time CAS hold time CAS to RAS precharge time Transition time (rise and fall) Refresh period tRC tRP tRAS tCAS tASR tRAH tASC tCAH tRCD tRAD tRSH tCSH tCRP tT tREF 110 40 60 15 0 10 0 15 20 15 15 60 5 3 - ns ns ns ns ns ns ns ns ns ns ns ns ns ms 7
Read Cycle
Access time from RAS Access time from CAS Access time from column address Column address to RAS lead time Read command setup time Read command hold time Read command hold time referenced to RAS CAS to output in low-Z Output buffer turn-off delay tRAC tCAC tAA tRAL tRCS tRCH tRRH tCLZ tOFF - - - 30 0 0 0 0 0 60 15 30 - - - - - 15 ns ns ns ns ns ns ns ns ns 11 11 8 12 8, 9 8, 9 8,10
Semiconductor Group
7
HYM 364020S/GS-60 4M x 36-Bit
AC Characteristics (cont' d) 5)6) TA = 0 to 70 C,VCC = 5 V 10 %, tT = 5 ns Parameter
Symbol
Limit Values -60 min. max.
Unit
Note
Early Write Cycle
Write command hold time Write command pulse width Write command setup time Write command to RAS lead time Write command to CAS lead time Data setup time Data hold time tWCH tWP tWCS tRWL tCWL tDS tDH 10 10 0 15 15 0 10 - - - - - - - ns ns ns ns ns ns ns 14 14 13
Fast Page Mode Cycle
Fast page mode cycle time CAS precharge time Access time from CAS precharge RAS pulse width CAS precharge to RAS Delay tPC tCP tCPA tRAS tRHCP 40 10 - 60 35 - - 35 200k - ns ns ns ns ns 7
CAS-before-RAS Refresh Cycle
CAS setup time CAS hold time RAS to CAS precharge time Write to RAS precharge time Write hold time referenced to RAS tCSR tCHR tRPC tWRP tWRH 10 10 5 10 10 - - - - - ns ns ns ns ns
Semiconductor Group
8
HYM 364020S/GS-60 4M x 36-Bit
Notes:
1) All voltages are referenced to VSS. 2) ICC1, ICC3, ICC4 and ICC6 depend on cycle rate. 3) ICC1 and ICC4 depend on output loading. Specified values are measured with the output open. 4) Address can be changed once or less while RAS = VIL. In the case of ICC4 it can be changed once or less during a fast page mode cycle (tPC). 5) An initial pause of 200 s is required after power-up followed by 8 RAS cycles of which at least one cycle has to be a refresh cycle, before proper device operation is achieved. In case of using internal refresh counter, a minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required. 6) AC measurements assume tT = 5 ns. 7) VIH (min.) and VIL (max.) are reference levels for measuring timing of input signals. Transition times are also measured between VIH and VIL. 8) Measured with a load equivalent to 2 TTL loads and 100 pF. 9) Operation within the tRCD (max.) limit ensures that tRAC (max.) can be met. tRCD (max.) is specified as a reference point only: If tRCD is greater than the specified tRCD (max.) limit, then access time is controlled by tCAC. 10)Operation within the tRAD (max.) limit ensures that tRAC (max.) can be met. tRAD (max.) is specified as a reference point only: If tRAD is greater than the specified tRAD (max.) limit, then access time is controlled by tAA. 11)Either tRCH or tRRH must be satisfied for a read cycle. 12)tOFF (max.) define the time at which the outputs achieve the open-circuit condition and are not referenced to output voltage levels . 13)tWCS is not a restrictive operating parameter. This is included in the data sheet as electrical characteristics only. If tWCS > tWCS (min.), the cycle is an early write cycle and the I/O pin will remain open-circuit (high impedance) through the entire cycle. 14)These parameters are referenced to the CAS leading edge.
Semiconductor Group
9
HYM 364020S/GS-60 4M x 36-Bit
Package Outline
FRONT SIDE
107.95 101.19
3.38
3.18 22.86
8.89 max
R1.57
1.27 2.03 6.35 95.25
R 1.57 +/- 0.05 6.35 +/- 0.05
+/- 0.05
10.16
1.27
+0.10 -0.08
BACK SIDE
Detail of Contacts
0.25 max
2.54 min
1.27
1.04 +/- 0.05
Frontside : 4Mx4 DRAMs Backside : 4Mx1 DRAMs
Tolerances : +/- 0.13 unless otherwise specified
L-SIM7212.DRW/WMF
7.23 min
6.35
GLS05835
Module Package, L-SIM-72-12 (Single in-Line Memory Module)
Semiconductor Group
10

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